Generally, to integrate III-V materials on a silicon (“Si”) substrate aligned along a <100> crystal orientation (“Si (100)”) for system-on-chip (“SoC”) high voltage and radio frequency (“RF”) devices with Complementary Metal Oxide Semiconductor (“CMOS”) transistors, great challenges arise due to dissimilar lattice properties of the III-V materials and silicon. Typically, when a III-V material is grown on a silicon (“Si”) substrate defects are generated due to the lattice mismatch between the III-V material and Si. These defects can reduce the mobility of carriers (e.g., electrons, holes, or both) in the III-V materials.
Currently, integration of GaN (or any other III-N material) on Si (100) wafer involves the use of thick buffer layers (>1.5 um) and starting miscut Si (100) wafer with 2-8° miscut angle to obtain a low enough defect density layer for the growth of the device layers. Typically, integration of GaN (or any other III-N material) on Si (100) wafer involves a blanket epitaxial growth process which occurs over the entire wafer and is not selective area or pattern specific. Additionally, current techniques do not provide a pathway for co-integration of both GaN transistors and Si CMOS circuits in close proximity to each other.